Intel’s top chip engineers gave a rare briefing on Tuesday about the company’s approach to designing its family of chips under the banner of Intel architecture, and they promised that good things are coming despite some well-publicized setbacks.
In the briefing, the engineers lifted the veil on the microarchitecture — the blueprint for its processor — for the upcoming Tiger Lake 10-nanometer CPU (central processing unit), which is slated to be unveiled in products on September 2.
The briefing was the first detailed technical discussion about Intel’s innovation plans since 2018. One reason it has been so long is that Intel has had a hard time getting its chip manufacturing right. This has held up its efforts to compete with rival Advanced Micro Devices, which has enjoyed a historic period of growth in the past three years.
Intel’s designers said they were proud of Tiger Lake. But they weren’t allowed to talk about the exact performance for the new processors, which are built in a 10-nanometer process and will be known as Intel’s 11th Generation CPU processors. The CPUs will be paired with Xe graphics and will benefit everything from servers to games. They will also sport a transistor redesign with something Intel calls SuperFin technology, said Raja Koduri, senior vice president and chief architect, in a briefing.
Intel recently announced it would have to delay its eagerly anticipated 7-nanometer manufacturing process, news that sent the company’s stock price down. The issues could also mean more delays for upcoming chips, such as the family of DG1 graphics chips for both servers and gaming devices. In the wake of the delay, one of Intel’s top executives, Venkata “Murthy” Renduchintala, resigned from his post. Renduchintala had appeared at Intel’s previous Architecture Day in 2018 and had been considered one of the candidates for the CEO job Bob Swan landed after Brian Krzanich left in 2018.
In June, well-known chip architect Jim Keller left Intel for personal reasons. That was a blow, as Intel made a big deal when Keller — who helped AMD design the chips that are giving it an architectural advantage over Intel today — joined two years ago. His relatively brief tenure didn’t even leave enough time for Keller-led innovations to make it into products.
The holdup with 7-nanometer manufacturing — which makes chips cheaper, faster, and smaller — followed a delay with the previous 10-nanometer generation. AMD was, however, able to exploit that previous gaffe by using external chip producers.
Koduri said Intel is attempting to change how it couples chip design and manufacturing so its chip products won’t depend on a particular manufacturing process being developed on time. Intel has hinted that it could use outside manufacturers — such as contract chip manufacturer TSMC — to make its chips in their own factories. Koduri referred to this new strategy as “system-resilient design.”
He said Intel remains focused on six pillars of processor innovation, which it can move forward as each pillar comes up for renewal in the company’s product pipeline. Those pillars include heavy development efforts in 3D packaging, chip architecture, 3D flash memory, interconnects, security, and software.
“We have a wonderful history of delivering breakthrough hardware,” said Koduri, who noted the company has more than 100,000 engineers. “You will see the progress we are making on this inspiring journey. Some of the smallest things they have created have led to some of the biggest impacts on the world.”
Intel recognizes that advantages from chip manufacturing are coming more slowly than in the past, so it has to focus more on the design, or architecture of its chips, to get performance, cost, and energy efficiency improvements. The company has launched the first processors using its Foveros 3D packaging technology, which can stack chips in ways that confer the advantage of three-dimensional efficiency. Koduri first described that technology during the 2018 Architecture Day event.
Willow Cove core
Intel’s Tiger Lake processors use the Willow Cove core (a successor to the previous Sunny Cove design), which was redesigned with a larger secondary memory and improvements in both memory and data pathways. As part of Tiger Lake, Willow Cove will enable Intel to field chips with four to eight cores, in competition with AMD’s eight to 16 cores. Intel will make the argument that its cores can do more work.
Intel also argued that its new SuperFin transistors built with its 10-nanometer manufacturing process will deliver as much improvement as if the company had shifted to the new generation on time. The transistors enable Intel to operate the Tiger Lake chip on a dramatically lower voltage, allowing it to operate faster and more efficiently.
Improvements from the transistors also gave the designers more headroom to add features that could affect improvements. As an example, Intel’s cores have 96 execution units compared to its previous 64 — and those will operate faster.
“The results of these engineering investments have greatly exceeded our expectations,” said Boyd Phelps, vice president of the client engineering group at Intel, in the briefing. “We delivered unprecedented leaps in performance. I’m thrilled to announce we have delivered on our ambitions.”
(Of course, we don’t know exactly what the performance of Tiger Lake is yet). Intel also talked a lot about its 3D NAND flash memory, field programmable gate arrays, AI processors, and other innovations during the briefing. But excitement is high around the long-awaited graphics chips.
Lisa Pearce, vice president for graphics and software, said Intel is working hard on its Xe graphics processor units (GPUs) in a variety of markets, including high-end servers, datacenter AI, gaming, mid-range computers, and entry-level computers.
Intel said Xe graphics will enable games such as Battlefield 1 to run at higher frame rates with more detailed scenery while consuming much less power. Koduri showed side-by-side videos of the improvements compared to the prior Gen11 integrated graphics but didn’t disclose the exact performance numbers. Xe graphics will span from low-end machines that use basic graphics capabilities to the high end, where rivals AMD Radeon and Nvidia GeForce are the main competitors.
The Xe graphics coupled with Tiger Lake will target lower-end computers with integrated graphics, which ship in the hundreds of millions of units. Features such as game sharpening can make details pop better in games, and these improvements running on Intel’s own rewritten DX11 graphics drivers at the low end will pressure AMD and Nvidia to raise the bar on the high end.
Intel is also working on standalone graphics chip DG1, its first discrete GPU in more than 20 years and an attempt to knock Nvidia and AMD out of the game. Intel is beginning to share software that will run on DG1 and help developers learn how to create applications that run on the DG1, which will be a highly parallel chip. One product with four DG1 chips, or four tiles, will be targeted at the datacenter.
Koduri said single-precision floating-point performance is around 40 teraflops, compared to 20 teraflops for the best GPU in the market today. He also said DG1 will support real-time ray tracing, which makes for realistic shadows and lighting in games.
“We will ship DG1 this year, and we will share many details on this chip soon,” Koduri said. “The really cool thing here is we are able to achieve this scaling with a single hardware design and a single software stack.”
Intel is using the same design to build a gaming-optimized GPU, targeted for shipment in 2021.
As for gamers, Koduri said, “The good news is we haven’t forgotten. We know enthusiast gamers are the hardest ones to impress. This GPU is now in our labs as we speak.”